The present inventive concept relates to semiconductor devices, and more particularly, to multi-layer or three dimensional (3D) semiconductor devices and methods of fabricating same.
The demand for inexpensive semiconductor devices having high performance continues to drive integration density. In turn, increased integration density places greater demands on semiconductor fabrication processes. The integration density of two-dimensional (2D) or planar-type semiconductor devices is determined in part by the area occupied by the individual elements (e.g., memory cells) making up the constituent integrated circuitry. The area occupied by individual elements is largely determined by the sizing parameters (e.g., width, length, pitch, narrowness, adjacent separation, etc.) of the patterning technology used to define the individual elements and their interconnections. In recent years, the provision of increasingly “fine” patterns has necessitated the development and use of very expensive pattern formation equipment. Thus, the dramatic improvements in the integration density of contemporary semiconductor devices has come at considerable cost, and yet designers continue to run up against the practical boundaries of fine pattern development and fabrication.
As a result of the foregoing and a number of related fabrication challenges, increased integration density has more recently demanded the development of multi-layer or so-called three-dimensional (3D) semiconductor devices. For example, the single fabrication layer conventionally associated with the memory cell arrays of 2D semiconductor memory devices is being replaced by a multi-fabrication layer or three-dimensional (3D) arrangements of memory cells.